../src/riscv_core/csr_regfile.v
../src/riscv_core/decoder.v
../src/riscv_core/execute.v
../src/riscv_core/fetch.v
../src/riscv_core/interrupt.v
../src/riscv_core/mem_access.v
../src/riscv_core/regfile.v
../src/riscv_core/riscv_top.v
../src/riscv_core/top_ctrl.v
../src/riscv_core/write_back.v
../src/soc/riscv_mem.v
../src/soc/riscv_rib.v
../src/soc/soc_riscv_top.v
../src/tb/riscv_tb_top.v
